1. Field of the Invention
The present invention relates to a semiconductor device having a high dielectric strength MOS transistor.
2. Description of the Prior Art
Some conventional semiconductor devices include a semiconductor substrate having a tub of conductivity type different from the counterpart of the semiconductor substrate, the tub formed within the semiconductor substrate. In the tub, a drift layer is formed which has the same conductive type as the semiconductor substrate. An embodiment of such conventional semiconductor device is a P-type high dielectric strength MOS transistor is shown in FIG. 7.
FIG. 7 is a view illustrating a general construction of the semiconductor device. As a semiconductor substrate, a P-type silicon substrate 1 is used. This p-type silicon substrate 1 defines an active region by forming a select oxide film 11 comprising SiO.sub.2 on the silicon substrate 1. On this active region is formed a gate oxide film 13 comprising SiO.sub.2. On the gate oxide film 13 is further formed a gate electrode 14 formed of polysilicon. Further within this silicon substrate 1 is formed a tub 35 constituting a n.sup.- type impurity diffusion layer. Within this tub 35 below the select oxide film 11 is formed drift layers 12 constituting a P-type impurity diffusion layer. Further within this tub 35 and on the surface of the silicon substrate 1 is formed source/drain regions 15 and 16, the drain region 16 is connected to the drift layers 12. The concentration of impurity in the tub 35 gradually decreases from the surface of the silicon substrate 1 to the inside thereof. Reference Numeral 36 designates an isoline connecting the points of the same impurity concentration inside the tub. On the other hand, on the silicon substrate 1 including the gate electrode 14 is laminated a CVD SiO.sub.2 film 17. On this CVD SiO.sub.2 film 17 is formed a contact hole extending through to the silicon substrate 1. Through this contact hole, a source electrode 18 and a drain electrode 19 are formed each connected to the source/drain regions 15 and 16.
In the above semiconductor device, an electric field is generated between the drift layers 12 and the tub 35. Then the strength of this electric field determines the reverse dielectric strength. To raise the reverse dielectric strength, it is necessary to lower the impurity concentration of the tub 35.
FIG. 6 shows a relationship between the reverse dielectric strength and the impurity concentration of the tub 35. FIG. 6 shows that the reverse dielectric strength decreases along with an increase in the impurity concentration of the tub 35.
However, lowering the impurity concentration or the tub 35 in order to raise the reverse dielectric strength generates the following drawback in the above semiconductor device.
One drawback is that current flows between the source/drain regions 15 and 16 even if the channel is not formed between them, and a punch-through is liable to occur. When punch-through is liable to occur, the gate length (X in FIG. 7) which corresponds to the distance between the drain and source is increased. Thus the size of the transistors becomes larger.
Another drawback is that when a low voltage driving transistor is provided along with the high dielectric strength MOS transistor on the same silicon substrate 1, the tub for forming the low voltage driving transistor and the tub 35 for forming the high dielectric strength MOS transistor have different impurity concentration. Consequently these two tubs must be formed separately, and the process for preparing them becomes more complicated.